1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv509 features hvcmos ? technology output voltage up to +200vshift register speed 500khz @ v dd = 2.0v 16 high voltage outputshigh voltage backplane driver cmos input levels applications multiple segment el display piezoelectric transducer driver braille driver ?? ? ? ? ? ? ? ? typical application circuit 16-channel serial to parallel converter with high voltage backplane driver and push-pull outputs general description the hv509 is a 200v, 16-channel serial to parallel converter. the high voltage outputs and the backplane driver are designed to source and sink 1.0ma. the high voltage outputs are controlled by a 16-bit serial shift register, followed by a 16-bit latch. data is shifted through the shift registers during the low to high clock transition. a data output buffer is provided for cascading multiple devices. data is transferred to the 16-bit latch when a logic level low is applied to the le input. data is stored in the latch when le is high. output states are controlled by the data in the latch and by the pol pin. micro processor el segment panel low voltage power supply high voltage power supply d in clk le pol d out to d in of another hv509 for cascading (if needed) 16 supertex hv509 hv out 1 hv out 16 bp v bias high voltage level translators & push-pull output low voltage shift register latches downloaded from: http:///
2 hv509 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com ordering information device package option 32-lead qfn 5.00x5.00mm body 1.00mm height (max) 0.50mm pitch hv509 HV509K6-G -g indicates package is rohs compliant (green)absolute maximum ratings parameter value logic supply, v dd -0.5v to 7.0v high voltage supply, v pp 215v translator supply voltage, v bias -0.5v to 7.0v logic input levels -0.5v to v dd + 0.5v operating junction temperature -40c to +125c storage temperature range -65c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. pin con?guration operating supply voltages and conditions sym parameter min typ max units conditions v dd logic supply voltage 2.0 3.0 5.5 v --- v bias level translator supply voltage 2.6 - 6.6 v --- v pp positive high voltage supply 50 - 200 v --- v ih high-level input voltage 0.9v dd - v dd v --- v il low-level input voltage 0 - 0.1v dd v --- t a operating temperature 0 - +70 c --- notes: 1. external ground noise reduction circuit will be provided by design upon characterization.2. power-up sequence should be the following*: 1. apply ground 2. apply v dd 3. set all inputs (d in , clk, le , pol) to a known state 4. apply v bias 5. apply v pp 3. power-down sequence should be the reverse of the above. *this power up sequence requires an external high voltage diode between vdd and vpp. without the dio de, power up vpp to a vdd level ?rst to bias the silicon substrate. after all other signals are powered, ?nish raising the v pp to its ?nal level. 1 32-lead qfn (top view) pads are at the bottom of the package. exposed heat slug is at v pp potential. 32 product marking hv509 llllll yyww aaaccc l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = green packaging 32-lead qfn (k6) downloaded from: http:///
3 hv509 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com dc electrical characteristics (over operating supply voltages and temperature, unless otherwise noted) sym parameter min typ max units conditions i dd v dd supply current - - 1.0 ma f clk = 500khz i ddq quiescent v dd supply current - - 10 a all logic inputs = v dd or 0v i bias v bias supply current - - 100 a all hv outs switching at 1khz. peak i bias = 200ma with all channels switching i biasq quiescent v bias current - - 10 a no hv out switching i ppq quiescent v pp supply current - - 100 a v pp = 200v, outputs are static i ih high-level logic input current - - 10 a v ih = v dd i il low-level logic input current - - -10 a v il = 0v v oh high level output hv out & bp v pp - 12v - - v ihv out = -1.0ma, v pp = +200v v pp - 12v -- - v ihv out = -1.0ma, v pp = +50v d out v dd - 1.0v - - v id out = -1.0ma v ol low level output hv out & bp - - 12 v ihv out = 1.0ma, v bias = 5.4v, v pp = +50 to +200v d out - - 1.0 v id out = 1.0ma c din logic input capacitance - - 10 pf --- c dout logic output capacitance - - 10 pf --- ac electrical characteristics (over operating supply voltages and temperature, unless otherwise noted) sym parameter min typ max units conditions f clk clock frequency 0 - 500 khz --- t c clock high / low pulse width 1.0 - - s --- t su data setup time before clock rises 50 - - ns --- t h data hold time after clock rises 50 - - ns --- t cle le from clk setup time 15 - - ns --- t wle le pulse width 100 - - ns --- t dd clock negative edge to d out delay - - 150 ns c ldout = 50pf, (c ldout includes c din and c dout ) t phv delay time from inputs for hv out / bp to start rise/fall - - 500 ns v pp = 200v, v bias = 5.4v t or hv output / bp rise time - - 300 s c l = 1500pf, v pp = 200v t of hv output / bp fall time - - 300 s c l = 1500pf, v bias = 5.4v, v pp = 200v t oc width of pol pulses t phv + t or /t of - - s --- downloaded from: http:///
4 hv509 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com input and output equivalent circuits v dd input gnd v dd data out v pp hv out hvgnd gnd logic inputs high voltage outputs logic data output v bias the v bias supply operates from 2.6v to 6.6v. it is the gate drive voltage for all of the output n-channel mosfets. this allows the output peak current sink to be set by varying the v bias voltage. a higher v bias voltage will increase the current sinking capability. if large peak currents are not required, v dd and v bias can be connected to the same power supply, provided they are both within the operating range. the operating v dd range is 2.0v to 5.5v. a plot showing the typical characteristics of i sink vs v bias is shown below. v bias supply 20.018.0 16.0 14.0 12.0 10.0 8.06.0 4.0 2.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6 .0 6.5 i sink (ma) v bias (v) typical hv out i sink vs v bias (v pp = 200v, c load = 1nf) downloaded from: http:///
5 hv509 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com switching waveforms downloaded from: http:///
6 hv509 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com functional block diagram level translator 16-bitlatch logic 16-bit shift register logic level translator level translator & buffer function table function inputs outputs d in clk le pol shift reg 1 2...16 hv outputs 1 2...16 bp d out load s/r h or l h x h or l ... ... x transfer data in latch x l l h * * .......... * * * .......... * l x l l l * * .......... * * * .......... * (b) h store data in latches x x h h ... ... l x x h l ... ... (b) h transparent mode l l h l ... l ... l h l h h ... h ... l invert mode x x h l ... ... (b) h x x x h h ... ... l x notes: h = high level, l = low level, x = irrelevant, = low-to-high transition = dependent on previous stages state before the last clk or last le low * = data at the last clk (b) = bar over all symbols downloaded from: http:///
7 hv509 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com pin description pin # function description 1 hv out 12 high voltage push-pull output 2 hv out 11 high voltage push-pull output 3 hv out 10 high voltage push-pull output 4 hv out 9 high voltage push-pull output 5 hv out 8 high voltage push-pull output 6 hv out 7 high voltage push-pull output 7 hv out 6 high voltage push-pull output 8 hv out 5 high voltage push-pull output 9 hv out 4 high voltage push-pull output 10 hv out 3 high voltage push-pull output 11 hv out 2 high voltage push-pull output 12 hv out 1 high voltage push-pull output 13 nc no connect 14 vpp high voltage supply 15 gnd logic ground 16 nc no connect 17 din data in 18 nc no connect 19 clk clock input logic 20 vdd logic supply voltage 21 pol polarity bar input logic 22 le latch enable bar input logic 23 nc no connect 24 dout data out 25 nc no connect 26 vbias level translator bias voltage 27 hvgnd high voltage ground 28 bp high voltage backplane output 29 hv out 16 high voltage push-pull output 30 hv out 15 high voltage push-pull output 31 hv out 14 high voltage push-pull output 32 hv out 13 high voltage push-pull output downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receive s an adequate product liability indemnification insuran ce agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for p ossible omissions and inaccuracies. circuitry and s pecifications are subject to change without notice. for the lates t product specifications refer to the supertex inc. website: http//www.supertex.com. ?2008 all rights reserved. unauthorized use or reproduct ion is prohibited. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com 8 hv509 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the la test package outline information go to http://www. supertex.com/packaging.html .) doc.# dsfp-hv509 a091908 32-lead qfn package outline (k6) 5.00x5.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 4.85* 1.05 4.85* 1.05 0.50 bsc 0.30 ? 0.00 0 o nom 0.90 0.02 0.25 5.00 - 5.00 - 0.40 ? - - max 1.00 0.05 0.30 5.15* 3.55 ? 5.15* 3.55 ? 0.50 ? 0.15 14 o jedec registration mo-220, variation vhhd-6, issue k, june 2006. * this dimension is not speci?ed in the original jedec drawing. the value listed is for reference on ly. ? this dimension is a non-jedec dimension. drawings not to scale. supertex doc. #: dspd-32qfnk65x5p050, version b090808. notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. the inner tip of the lead may be either rounded or square. 1.2. 3. seating plane top view side view bottom view a a1 d e d2 e b e2 a3 l l1 view b view b 1 note 3 note 2 note 1(index area d/2 x e/2) note 1(index area d/2 x e/2) 1 32 32 downloaded from: http:///
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